The present application claims priority under 35 U.S.C. xc2xa7119 to Japanese Application No. 2000-208003 filed on Jul. 10, 2000, which is hereby incorporated by reference in its entirely for all purposes.
1. Field of the Invention
The present invention relates to an integrated circuit. In particular, the invention relates to an inverter circuit.
2. Description of the Related Art
An inverter is sometimes used as a delay circuit in an integrated circuit. A conventional inverter includes one N channel MOSFET (NMOS) and a P channel MOSFET (PMOS), and an inputted signal is inverted by the inverter. A delay of signal is caused during this inverting operation.
However, the delay circuit, which is composed by conventional inverters, has to have a plurality of conventional inverters according to a delay time and a logic level of an outputted signal. Therefore, an area of the delay circuit becomes wide. It is difficult to reduce the area of the delay circuit by using conventional inverters.
An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.